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  • Salvador20

    őstag

    nekem ilyen beállítások vannak memory timing alant, sztem ezért nem vágom, hogy merre vok arcal, amikor a biosba belépek
    Trc(11,12,13~26)

    Twr(3,4,5,6)

    Trrd(2,3,4,5)

    Trwt(2,3,4,5~9)

    Trtp(2/4, 3/5)

    Twrrd(0,1,2,3)

    Twrwr(1,2,3)

    Trdrd(2,3,4,5)

    Tref(7.8 us, 3.9 us)

    Trfc(0,1,2,3)

    DRAM Termination(auto, disabled, 75 ohms, 150ohms, 50 ohms)

    Max Async Latecy(auto, 0ns, 1ns, 2ns, ~25ns)

    R/W Queue Bypass(2X,4X,8X,16X)

    Dynamic Idle Cycle Counter(enabled, disabled)

    Idle Cycle Limit(auto, 0cycles, 4cycles,8cycles,16cycles,32cycles,128cycles,256cycles,512cycles,1024cycles)

    DCQBypass Maximum(0X,1X,2X,~15X)

    DRAM Burst Length(64-byte, 32-byte)

    DRAM Bank Interleaving(enabled,disabled)
    CHA/CHB CKE Delay(no delay, 1/64MEMCLK delay, 2/64MEMCLK delay, 3/64MEMCLK
    delay,31/64MEMCLK delay)

    CHA/CHB Setup time(1/2 MEMCLK, 1 MEMCLK)

    CHA/CHB C/S ODT Fine Delay(1/64MEMCLK delay~31/64MEMCLK delay)

    CHA/CHB C/S Setup Time(1/2MEMCLK, 1MEMCLK)

    CHA/CHB Add/CMD Fine delay (1/64MEMCLK delay~31/64Delay)

    CHA/CHB Add/CMD Setup Time(1/2MEMCLK,1 MEMCLK

    Read DQS Timing Contol(No delay, 1/96 MEMCLK delay~47/96 MEMCLK delay)

    Write data timing control(no delay, 1/96 MEMCLK delay~47/96 MEMCLK delay)

    DQS Receiver Enable Timing( 1ps,50ps, 100ps, 150ps~8700ps)

    CHA/CHB CKE Drive SDtrength(1X,1.25X,1.50X,2X)

    CHA/CHB C/S ODT Drive Strength(1X,1.25X,1.50X,2X)

    CHA/CHB Add/CMD DriveStrength(1X,1.25X,1.50X,2X)

    MEMCLK Drive Strength(0.75X, 1.00X, 1.25X, 1.50X)

    Data Drive Strength(0.75X, 1.00X, 1.25X, 1.50X)

    DQS Drive Strength(0.75X, 1.00X, 1.25X, 1.50X)

    DRAM Drivers Weak Mode(auto, normal ,weak)


    Hát ennyi, nagyjából semmit nem értek belőle

    Huh, mire kimásoltam a kézikönyvemből :)

    [Szerkesztve]

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