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• #8581 S_x96x_S addikt Petykemano #8580

  Új Válasz 2023-02-02 15:37:43 #8581

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  S_x96x_S

  addikt

  válasz Petykemano #8580 üzenetére

  > Ez persze nem hivatalos, de két érdekes információmorzsa:
  > - a Zen4 2 negyedéved csúszott a CXL integráció céljából.

  ha jól tudom, a 2 negyedéves csúszás Forrest Norrod publikusan felvállalt döntése volt,
  valószínüleg a Cloud-os ügyfelek nyomására .. ( Type 3 memory devices támogatása )
  
  "
  Forrest Norrod: First of all, we really like CXL. I delayed Genoa to get CXL in it.
  We really like UCI, but I think that it is going to be a couple of generations before it gets to the point you can have high bandwidth and relatively low latency connections between discrete functions.
  If you can put a clean boundary around a function, I think that you can connect them with UCI fairly easily. And that is not first generation, but second generation – that’s sort of the way these standards go. But if you need to use chiplets to break up a function and then scale that function with multiple dies, the interconnect for that sort is so different. It is difficult to tunnel stuff like that through a standard interface of any type. If you are breaking up a function, you really want 20,000 wires, and you don’t want to impose a protocol and you don’t want to impose any sort of latency cost on top of that."
  https://www.nextplatform.com/2022/10/03/the-steady-hand-guiding-amds-prudently-expanding-datacenter-business/

  -------------------

  As Norrod explained to us several weeks ago, Genoa was delayed by two quarters to intersect the CXL disaggregated memory standard, but AMD never dreamed that it would be beating Intel’s “Sapphire Rapids” Xeon SPs to market. Genoa was timed to come to market around the same time as Intel was expected to have its “Granite Rapids” Xeon SPs to market, which are now coming in 2024.
  https://www.nextplatform.com/2022/11/10/amd-genoa-epyc-server-cpus-take-the-heavyweight-title/
  --------------------------

  AMD generally supports CXL 1.1 but supports CXL 2.0 for Type 3 memory devices. We exclusively detailed this feature support level here.
  "Type 3 is what the ecosystem wanted." ( Kevin Lepak, Genoa Server SOC Chief Architect )
  Genoa was delayed 2 quarters to add this feature, and we believe that was the correct decision.
  https://www.semianalysis.com/p/amd-genoa-detailed-architecture-makes

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