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• #386 P.H. senior tag DRB #383

  Új Válasz 2010-04-19 19:02:55 #386

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  P.H.

  senior tag

  válasz DRB #383 üzenetére

  AMD-re vannak - nem konkrét - adatok ([link]; C3-as és Istanbul-ok adatokat is tartalmaz; hosszú lesz , a feszültségállítás a bonyolultabb és a sokkal hosszadalmasabb, itt két lehetőség van BIOS-ban felprogramozva:
  - slammed: közvetlenül kapcsol két feszültség között (úgy tűnik ezt nincs K8-on)
  - ramped vagy stepped: egyesével végigkapcsolgatja az értékeket 0,0125V-onként, amíg eléri a célfeszültséget

  Hardware-Initiated Voltage Transitions
  VDD and VDDNB voltage levels may be transitioned during state changes involving boot, reset, P-state, and stop-grant. Voltage transitions may be slammed or stepped as specified by [The Power Control Miscellaneous Register] F3xA0[SlamVidMode]. F3xA0[SlamVidMode]=1 means the processor sends a single VID code to the voltage regulator. The voltage stabilization time is specified by F3xD8[VSSlamTime] and, if altvid is enabled, F3xDC[AltvidVSSlamTime, SlamTimeMode]. F3xA0[SlamVidMode]=0 means the processor sends multiple VID codes one increment at a time until the destination VID is reached.

  Software-Initiated Voltage Transitions
  The processor supports direct software VID control using [The COFVID Control Register] MSRC001_0070. The setting for F3xA0[SlamVidMode] determines the sequence used for direct VID control.

  P-state changes normally include a COF change and a VID change. If the P-state number is increasing (to a lower-performance state), then the COF is changed first, followed by the VID change. If the P-state number is decreasing, then the VID is changed first followed by the COF. VID changes may be slammed or ramped; see 2.4.1.8 [Hardware-Initiated Voltage Transitions].

  P-state changes that include VID changes may take 100’s of microseconds to complete. Once the processor has initiated a VID change for a domain, it completes it regardless of what commands are received while the Pstate change takes place. If multiple commands are issued that affect the P-state of a domain prior to when the processor initiates the change of the P-state of that domain, then the processor operates on the last one issued.

  Közvetlen átmenet módja:
  SlamVidMode: slam voltage ID mode. Read-write. This specifies the voltage transition type when changing P-state. 1=The voltage is slammed. 0=The voltage is stepped. This bit is normally set if the regulator includes built-in output voltage slew rate control. It is required to be programmed to the same state in all nodes.

  Közvetlen átmenet ideje:
  VSSlamTime: voltage stabilization slam time. Read-write. Cold reset: 000b. Specifies the time to wait for voltage stabilization if a new VID is provided to the voltage regulator without ramping. See 2.4.1.8 [Hardware-Initiated Voltage Transitions]. If in SVI mode, then this time measures the period after the end of the SVI command.
  Bits Time
  000b 10 microseconds
  001b 20 microseconds
  010b 30 microseconds
  011b 40 microseconds
  100b 60 microseconds
  101b 100 microseconds
  110b 200 microseconds
  111b 500 microseconds
  BIOS should program this field according to the following equation: VSSlamTime = x * [P0 voltage - Pmin voltage] where x=.4us/mV for server and desktop processors and x=.2us/mV for mobile processors. The VSSlamTime value should be rounded up to the nearest programmable time if necessary.

  Lépésenkénti átmenet lépéseinek ideje:
  VSRampTime: voltage stabilization ramp time. Read-write. Cold reset: 000b. Specifies the time to wait for voltage stabilization after each internal 7 bit VID increment (regardless of whether the SVI or PVI is used), if the voltage level is ramped. Refer to section 2.4.1.6 [VID Encodings] for internal 7 bit VID code to PVI VID encodings. If in SVI mode, this time measures the period from the end of each SVI command to the start of the next SVI command. See 2.4.1.8 [Hardware-Initiated Voltage Transitions].
  Bits Time
  000b 10 microseconds
  001b 20 microseconds
  010b 30 microseconds
  011b 40 microseconds
  100b 60 microseconds
  101b 100 microseconds
  110b 200 microseconds
  111b 500 microseconds
  BIOS should set this field to 001b.

  Az órajelet egyszerűbb állítani:

  PllLockTime: PLL synchronization lock time. Read-write. If a P-state change occurs that applies a new FID to the PLL, this field specifies the time required for the PLL to lock to the new frequency. These bits are encoded as follows:
  000b 1 microsecond.
  001b 2 microseconds.
  010b 3 microseconds.
  011b 4 microseconds.
  100b 8 microseconds.
  101b 16 microseconds.
  110b Reserved.
  111b Reserved.
  For revision B, BIOS should set this field to 101b. For revision C and later, BIOS should set this field to 001b.

  Közvetlen számértékek nincsenek leírva, mivel BIOS-tól függ és változó desktop-ra ill. mobil platformra, lehet a képletekből számolgatni.

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