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• #5201 S_x96x_S addikt

  Új Válasz 2021-06-02 02:00:31 #5201

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  S_x96x_S

  addikt

  ISA architektúrák .. X86 vs. ARM

  RISC vs. CISC Is the Wrong Lens for Comparing Modern x86, ARM CPUs
  https://www.extremetech.com/computing/323245-risc-vs-cisc-why-its-the-wrong-lens-to-compare-modern-x86-arm-cpus

  AGner Fog
  "
  ISA is not irrelevant. The x86 ISA is very complicated due to a long history of small incremental changes and patches to add more features to an ISA that really had no room for such new features…
  The complicated x86 ISA makes decoding a bottleneck. An x86 instruction can have any length from 1 to 15 bytes, and it is quite complicated to calculate the length. And you need to know the length of one instruction before you can begin to decode the next one. This is certainly a problem if you want to decode 4 or 6 instructions per clock cycle! Both Intel and AMD now keep adding bigger micro-op caches to overcome this bottleneck. ARM has fixed-size instructions so this bottleneck doesn’t exist and there is no need for a micro-op cache.
  Another problem with x86 is that it needs a long pipeline to deal with the complexity. The branch misprediction penalty is equal to the length of the pipeline. So they are adding ever-more complicated branch prediction mechanisms with large branch history tables and branch target buffers. All this, of course, requires more silicon space and more power consumption.
  The x86 ISA is quite successful despite of these burdens. This is because it can do more work per instruction. For example, A RISC ISA with 32-bit instructions cannot load a memory operand in one instruction if it needs 32 bits just for the memory address."

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  és mégegy Kapcsolódó cikk az elmúlt hetekből -
  Emulációnál viszont az ARM(AArch64) - 2x annyi regiszterének és a 3 operandusos utasításkészletének van valami előnye.
  Valamint energiahatékonyabb is az M1. ( de ez az 5nm miatt is )
  
  "Temptation of the Apple: Dolphin on macOS M1"

  "AArch64 does have its advantages, though. Namely, the processors have 31 registers, compared to the 16 available in x86-64 processors. The PowerPC processor we are emulating has 32 registers, and while it is rare for all of them to be used within a single code block, more registers is always nice to have. Another difference is that AArch64 and PowerPC have 3 operand instructions while x86-64 only has two.

  PPC: A = B + C AArch64: A = B + C x86-64: A = B, A = A + C

  As you can see, it makes emulating some instructions much cleaner and easier than on our x86-64 JIT. Alright, enough with the boring details. How does the M1 hardware perform when put up against some of the beasts of the GameCube and Wii library? ..."

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