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  Új Válasz 2020-05-12 01:03:16 #3112

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  S_x96x_S

  addikt

  néha érdemes újraolvasgani ...

  The microarchitecture of Intel, AMD and VIA CPUs
  By Agner Fog. Technical University of Denmark.
  Copyright © 1996 - 2020. Last updated 2020-03-08.

  https://www.agner.org/optimize/microarchitecture.pdf

  22.3 The AMD Zen kernel
  The Ryzen processor put AMD back in the game after they had lagged behind Intel for
  several years. The Zen kernel has a throughput of five instructions per clock cycle, which is
  the record so far. The throughput is particularly high for 128-bit vector code. The Ryzen can
  calculate four 128-bit floating point vectors per clock cycle, or two 256-bit vectors.
  The high throughput places a higher burden on programmers and compilers to utilize the
  increased instruction level parallelism in single threaded applications. The core throughput
  is so high that it makes good sense to run two threads per core, unlike some other
  processors with less core throughput which are likely to see a serious performance drop
  due to the two threads competing for the limited resources.
  The new μop cache is an important improvement which removes the bottleneck of
  instruction fetching and decoding in most of the critical loops.
  The large caches at all levels is a particularly important improvement. But the cache
  bandwidth is limited to 32 bytes per clock which is less than the best competing Intel
  processors.

  -------------

  For many years, the RISC philosophy has been considered the best way to high
  performance. The Intel Core microarchitecture as well as the AMD design indicates a new
  trend away from RISC and back to the CISC principle. The RISC-like design of the P4 with
  its very long pipeline and long execution latencies was not convincing, and the trace cache
  appears to have been inefficient. The advantages of going back to CISC design are
  threefold:
  1. The compact CISC code gives better utilization of the limited code cache area.
  2. Fewer μops per instruction gives higher bandwidth in the pipeline.
  3. Fewer μops per instruction gives lower power consumption.
  The main disadvantage of a CISC design is that instruction decoding becomes a bottleneck.
  The AMD processor has a higher decoding bandwidth than the Intel design because of the
  technique of storing instruction boundaries in the code cache. The Intel design is still limited
  to a decoding rate of 16 bytes of code per clock cycle, which is insufficient in many cases.

  -------------

  "There is a remarkable convergence between the Intel and AMD microarchitectures thanks
  to a patent sharing agreement between the two companies. Intel's stack engine and the
  mechanism for predicting indirect branches have been copied by AMD. We can also expect
  Intel to some day match AMD's 32-bytes instruction fetch rate

  There is unfortunately not always convergence on the instruction set extensions. Intel's
  SSE4.1 and SSE4.2 instruction sets are very different from AMD's SSE4.A and XOP
  (formerly known as SSE5), and the intersection between these two sets is quite small. Intel
  has never copied AMD's 3DNow instruction set which is now obsolete, but they have copied
  the successful x64 extension from AMD and a few other instructions. AMD has traditionally
  copied all Intel instructions, but sometimes with a lag of several years. Fortunately, AMD
  has revised their proposed SSE5 instruction set to make it compatible with the AVX coding
  scheme (as I have previously argued that it would be wise of them to do). The latest AMD
  processors now support Intel's AVX2 instruction set, including the 256-bit YMM vector
  registers. It may take several years before AMD supports AVX512.
  "

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