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Utoljára frissítve: 2014-04-25 14:12

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#6049 #90088192 törölt tag buherton #6048

Új Válasz 2020-03-27 06:55:16 #6049
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Összes hozzászólása itt Válaszok az összes hozzászólására itt Válaszok erre a hozzászólásra

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válasz buherton #6048 üzenetére

Köszönöm
Akkor természetesen jönnek az újabb kérdések, ha nem baj
Akkor a különböző részegységek funkcióit hogyan tudnám szeparálni.
Vagyis a mostani screen.c bol csináltam screen.h, így működik, de ha újabb .h-t hívok meg amiben egy előzőleg meghívott hardware.h benne van akkor megint ugyan az a probléma.
Tudom hülye kérdés, ilyen alap struktúra probléma, de fogalmam sincs ezekre hogyan keressek rá.
Amit el akarok erni: reszegysegenkent kulon fuggveny konyvtar vagy mi a fitty fene.(Nem tudom minek nevezzem)
Azt hogyan kellene strukturalni?
Közben kutakodtam, ezt találtam.
ez a hardware.h
#include "stdio.h" #include <string.h> #include <math.h> #include <p32xxxx.h> #include <D:\Program Files (x86)\Microchip\xc32\v2.30\pic32mx\include\peripheral\legacy\i2c_legacy.h> #define SYS_FREQ 80000000L #define FCY SYS_FREQ #define F_CPU SYS_FREQ #define DLY_COUNT (F_CPU/4000000) #define _delay_us( dly ) {unsigned int x=0,y=dly; while(y--){x=DLY_COUNT;while(x--);}} // DEVCFG3 // USERID = No Setting #pragma config FSRSSEL = PRIORITY_1 // SRS Select (SRS Priority 1) #pragma config FCANIO = OFF // CAN I/O Pin Select (Alternate CAN I/O) #pragma config FUSBIDIO = OFF // USB USID Selection (Controlled by Port Function) #pragma config FVBUSONIO = OFF // USB VBUS ON Selection (Controlled by Port Function) // DEVCFG2 #pragma config FPLLIDIV = DIV_2 // PLL Input Divider (2x Divider) #pragma config FPLLMUL = MUL_20 // PLL Multiplier (20x Multiplier) #pragma config UPLLIDIV = DIV_2 // USB PLL Input Divider (2x Divider) #pragma config UPLLEN = ON // USB PLL Enable (Enabled) #pragma config FPLLODIV = DIV_1 // System PLL Output Clock Divider (PLL Divide by 1) // DEVCFG1 #pragma config FNOSC = FRCPLL // Oscillator Selection Bits (Fast RC Osc with PLL) #pragma config FSOSCEN = ON // Secondary Oscillator Enable (Enabled) #pragma config IESO = ON // Internal/External Switch Over (Enabled) #pragma config POSCMOD = XT // Primary Oscillator Configuration (XT osc mode) #pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled) #pragma config FPBDIV = DIV_2 // Peripheral Clock Divisor (Pb_Clk is Sys_Clk/2) #pragma config FCKSM = CSDCMD // Clock Switching and Monitor Selection (Clock Switch Disable, FSCM Disabled) #pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576) #pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled (SWDTEN Bit Controls)) // DEVCFG0 #pragma config DEBUG = OFF // Background Debugger Enable (Debugger is disabled) #pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select (ICE EMUC2/EMUD2 pins shared with PGC2/PGD2) #pragma config PWP = OFF // Program Flash Write Protect (Disable) #pragma config BWP = OFF // Boot Flash Write Protect bit (Protection Disabled) #pragma config CP = OFF // Code Protect (Protection Disabled) //I/O Digital analog selection #define Analog_digital AD1PCFG //Screen Hardware Setup #define DISPLAY_Dir TRISE #define S_DATA_OUT LATE #define S_DATA_IN PORTE #define DISPLAY_CS1 LATGbits.LATG6 #define DISPLAY_CS2 LATDbits.LATD8 #define DISPLAY_RS LATGbits.LATG9 #define DISPLAY_RW LATDbits.LATD7 #define DISPLAY_EN LATDbits.LATD11 #define DISPLAY_CS1_Direction TRISGbits.TRISG6 #define DISPLAY_CS2_Direction TRISDbits.TRISD8 #define DISPLAY_RS_Direction TRISGbits.TRISG9 #define DISPLAY_RW_Direction TRISDbits.TRISD7 #define DISPLAY_EN_Direction TRISDbits.TRISD11 //Membrane #define JTAGEN DDPCONbits.JTAGEN #define MEMBRANE_MUTE LATBbits.LATB13 #define MEMBRANE_MAINS LATBbits.LATB14 #define MEMBRANE_ALARM LATBbits.LATB15 #define MEMBRANE_MUTE_Direction TRISBbits.TRISB13 #define MEMBRANE_MAINS_Direction TRISBbits.TRISB14 #define MEMBRANE_ALARM_Direction TRISBbits.TRISB15 //Analog inputs #define REF2_5 PORTBbits.RB0 #define MUX PORTBbits.RB1 #define BAT1_CURRENT PORTBbits.RB2 #define BAT2_CURRENT PORTBbits.RB3 #define CHARGER_CURRENT PORTBbits.RB4 #define CHARGER_VOLTAGE PORTBbits.RB5 #define LOAD_VOLTAGE PORTBbits.RB8 #define BRIDGE_VOLTAGE PORTBbits.RB9 #define VREQ PORTBbits.RB10 #define IREQ PORTBbits.RB11 #define REF2_5_DIRECTION TRISBbits.TRISB0 #define MUX_DIRECTION TRISBbits.TRISB1 #define BAT1_CURRENT_DIRECTION TRISBbits.TRISB2 #define BAT2_CURRENT_DIRECTION TRISBbits.TRISB3 #define CHARGER_CURRENT_DIRECTION TRISBbits.TRISB4 #define CHARGER_VOLTAGE_DIRECTION TRISBbits.TRISB5 #define LOAD_VOLTAGE_DIRECTION TRISBbits.TRISB8 #define BRIDGE_VOLTAGE_DIRECTION TRISBbits.TRISB9 #define VREQ_DIRECTION TRISBbits.TRISB10 #define IREQ_DIRECTION TRISBbits.TRISB11 void InitalizePorts_membrane() { JTAGEN=0; MEMBRANE_MUTE=1; MEMBRANE_MAINS=1; MEMBRANE_ALARM=1; MEMBRANE_MUTE_Direction =0 ; MEMBRANE_MAINS_Direction =0 ; MEMBRANE_ALARM_Direction =0 ; }; void InitalizePorts_display() { S_DATA_OUT=0; S_DATA_IN=0; DISPLAY_Dir=0; DISPLAY_CS1=1; DISPLAY_CS2=1; DISPLAY_RS=1; DISPLAY_RW=0; DISPLAY_EN=1; /* Command port direction settings */ DISPLAY_CS1_Direction =0 ; DISPLAY_CS2_Direction =0 ; DISPLAY_RS_Direction =0 ; DISPLAY_RW_Direction =0 ; DISPLAY_EN_Direction =0 ; }; void InitalizePorts_ADC() { Analog_digital= 0x10C0; AD1CON2 = 0x0000; AD1CON3 = 0x0000; // Configure ADC conversion clock AD1CSSL = 0x0000; // No inputs are scanned. Note: Contents of AD1CSSL are ignored when CSCNA = 0 IFS1CLR = 2; //Clear ADC conversion interrupt IEC1SET = 2; //Enable ADC conversion interrupt AD1CON1 = 0x00E0; // SSRC bit = 111 internal counter ends sampling and starts converting AD1CHS = 0b1111110011110000; // Connect RB2/AN2 as CH0 input in this example RB2/AN2 is the input AD1CSSL = 0; AD1CON3 = 0x0F00; // Sample time = 15Tad AD1CON2 = 0x0004; // Interrupt after every 2 samples //Analog PORT directions REF2_5_DIRECTION =1; MUX_DIRECTION =1; BAT1_CURRENT_DIRECTION =1; BAT2_CURRENT_DIRECTION =1; CHARGER_CURRENT_DIRECTION =1; CHARGER_VOLTAGE_DIRECTION =1; LOAD_VOLTAGE_DIRECTION =1; BRIDGE_VOLTAGE_DIRECTION =1; VREQ_DIRECTION =1; IREQ_DIRECTION =1; }; void I2C1_Init() { //***** I2C1 Hardware Init *****/ //-----Set pin drive modes----- //I2C - drive outputs so we can manually clear lines LATDbits.LATD9 = 1; //Start with bus in idle mode - both lines high LATDbits.LATD10 = 1; ODCDbits.ODCD9 = 1; //Open drain mode ODCDbits.ODCD10 = 1; TRISDbits.TRISD9 = 0; //SCL1 output TRISDbits.TRISD10 = 0; //SDA1 output /***** I2C1 Module start *****/ I2C1CON = 0x1000; //Set all bits to known state I2C1CONbits.I2CEN = 0; //Disable until everything set up. Pins will be std IO. I2C1BRG = 0x00C6; //set up baud rate generator I2C1CONbits.DISSLW = 0; //Enable slew rate control for 400kHz operation //IFS1bits.MI2C1IF = 0; //Clear I2C master int flag I2C1CONbits.I2CEN = 1; //Enable I2C } ;