Új hozzászólás Aktív témák
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dokar
addikt
K8L :
* Four processor cores
* independently changeable core voltages
* 48-bit memory addressing for massive memory subsystems
* official support for coprocessors connected via Hypertransport
* DDR2 support
* FB-DIMM support
* Memory mirroring support
* HyperTransport retry support
* New instructions LZCNT, POPCNT, EXTRQ/INSERTQ, MOVNTSD/MOVNTSS
* More agressive prefetching (16 bytes to 32 bytes)
* Out of order loads
* Z-RAM technology, projected to bring 4-5 times the cell density of current SRAM for CPU cache.
* Extension to the AMD64 instruction set during 2007; it is unclear whether AMD plans this for rev. G or rev. H chips.
* Large Level-3 cache, initially expected to be a minimum of 4MB shared cache between processing cores on a single die (each with independent second-level cache).
* Vector coprocessor support, which will bring several-fold FP/SIMD performance increase if a specialized processor is attached via coherent HyperTransport link in a specialized socket.
* Increased number of Hypertransport links per processor package to 5 (from 3 in current Opterons), and maximum socket count to 32; this will be implemented in either Rev. G or Rev. H Opterons.
* New SIMD instruction set and new, wide SIMD units; in a yet unspecified time frame.
* SSE4
Új hozzászólás Aktív témák
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