MSI 850 Pro2

One of our guests...

Whoever thinks there isn't a difference between a Pentium 4 and a Pentium 4 is wrong. Whoever may think that all Pentium 4 mainboards are created equal is also wrong. We are in the lucky position of being able to prove both of the statements above, as we have spent a few days together with a couple of P4 processors and motherboards. Out of the four, we will be mainly focusing on one of the motherboards - MSI's 850 Pro2 mainboard, built on a 4-layer design for Socket-423 Pentium 4 processors (aka Willamette), with the i850 chipset. Without giving away too much of our article, we can point a few things out, namely, that MSI is the first with a 4-layer P4 board and that is supposed to drive costs down. The 850 Pro2 also has a spectrum of features that the original 850 Pro didn't, but the ASUS P4T did... and since one of our P4 CPUs was from the "appropriate" batch, we were actually able to put these features to use.

What makes a Pentium 4 processor so good then? There are some general characteristics of P4 systems that make them "good", while there are several unique tricks that are not offered by everyone. Let's discuss the first type first, only very briefly. The most obvious thing here is FSB and bandwidth, which we have thoroughly discussed in our last Azza 633X-AD review. To put it simple, almost all recent platforms are limited by their FSB and/or memory interface. VIA's Pro266 chipset is trying to match DDR memory with an SDR FSB - the worst choice. VIA's KT133A has an SDR memory interface, but a DDR system bus (EV6). The new DDR chipsets for AMD processors seem to be much more balanced as they are offering a completely "Double Pumped" platform, as both the memory and the FSB operate at a double data rate (DDR). Intel tackled the problem in a major way with its i850 chipset and RDRAM support, while they did introduce a few "quirks" with their new CPU...

Pentium 4 basics

You will have to get used to this, but once something is invented in the computer business, it will later start to scale exponentially. You will always have double the same thing, then four times as much and so on. You can think CPU, AGP, memory speed or almost anything here. Remember the original 486DX CPU at 33MHz? Then we had 486DX2 at 66MHz and we didn't need much time to meet the - quite illogically named - 486DX4 CPU at 100MHz. The same happened with AGP 1X, 2X, 4X and now 8X, and the same is happening with the system bus, or FSB, for short (Actually, the 486DX2 is a perfect example here as it was the first CPU that had to separate its core frequency from the external bus. Before, the CPU and the bus were operating at the same speed, but with the introduction of a 66MHz, blazing fast processor :), that was no longer possible. So, the bus remained at 33MHz, while the CPU was using a double clock, internally. Nowadays, this is normal, as all CPUs come with a multiplier, which multiplies the external bus (FSB) to get the internal processor speed.). Only the scaling of the FSB is different, as clock rates are maxed out at 133MHz (as of yet), but manufacturers are pumping more and more data using that clock. More precisely:

• Current AMD platforms are all using the EV6 bus protocol licensed from the Alpha guys and operate at 100 or 133MHz, but use a DDR technique. So effective throughput is 200/266MHz if we translate that to a conventional SDR bus, but it is important to understand, that Athlons/Durons still operate their FSB at a 100 or 133MHz frequency!
• Intel is now doing the same for the first time, with Pentium 4. The FSB is operating at 100MHz, but data is sent a QDR (Quad-Data Rate) fashion, which means that four units of data are transferred with each clock. This is the same as if we used a 400MHz SDR bus, but the P4s still operate their FSB at a 100MHz frequency!

Most of you have known this for quite a while, but for the sake of completeness and a better understanding of what's coming, we wanted to make sure ;-). Marketing terms such as "unparallelled 400MHz FSB" can also be put to rest this way. Now for the Pentium 4 CPU and RDRAM: as with every CPU, the Pentium 4 also uses an internal multiplier to derive its final speed. Both of our 1.4GHz P4s use a 14X multiplier, which makes sense knowing that the FSB is running at 100MHz (if it did run at 400MHz, as you see on most mainboard boxes, 14 x 400MHz would give us a 5.6GHz CPU... not bad :-)). RDRAM is doing just the same: PC800 RDRAM is using a 4X multiplier AND is double clocked (so 4 x 2 x 100MHz = 800MHz), with PC700 and PC600 using 3.5X and 3X, respectively. As the external bus is 64 bits wide, the maximum usable bandwidth in the system is 8 bytes x 4 x 100MHz = 3200MB/sec. RDRAM has a 16 bits wide interface, but the i850 chipset is a dual-channel RDRAM implementation, so bandwidth with PC800 RDRAM is 4 x 2 x 100MHz x 2 bytes x 2 = 3200MB/sec, which just matches the FSB bandwidth. The upcoming nForce 420 (aka Crush 12) chipset from nVidia is using dual-channel DDR SDRAM and has a memory bandwidth of 4200MB/sec with PC2100 modules, but the system bus remains at 2.1GB/sec making for an unbalanced system (in reality, the most of that 4200MB/sec is needed by the integrated graphics). The balanced and very high maximum bandwidth is probably the strongest point of the whole Pentium 4 story.

We could take the route of starting to compare the P4 with the Athlon now, but we won't. To put it simple, there are some serious downsides of the P4 that most believers don't like to talk about. The die size of the current Pentium 4 CPUs is huge, 217 square millimeters, to be exact. That means P4 is running hot, it is a rather costy thing to produce and also implicitly means that there are some features of P4 that could have been implemented, but haven't. The FPU part simply sucks, with only one castrated pipeline feeding data - sure, there is SSE2 to compensate all that, but once it comes to pure FPU tasks, P4's almighty bandwidth isn't going to help much. L1 cache sizes are also a bit small (although they are FAST), with data cache being only 8KB and no code cache. The double pumped nature of the ALU (integer part) helps to hide the incredible penalties certain instructions generate, but surely doesn't take performance to new dimensions, like Intel claims. We sincerely hope that Intel will manage to repack all the stripped features once Northwood is released (and hope that the talks about 512KB L2 cache will prove false, as more L2 cache is NOT the best way to raise P4 performance now... integrating 512KB L2 cache eats up all available space for additional pipelines, etc.). If they do, AMD followers (and ASM coders :-)) will have a harder time trashing the P4. This is about as much as we wanted to say about performance compared to other solutions (read: AMD) and from now on, we will be focusing on the P4 hardware we had.

A cikk még nem ért véget, kérlek, lapozz!