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• #24 Maverick14 tag Elrood #22

  Új Válasz 2006-01-26 18:28:14 #24

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  Maverick14

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  válasz Elrood #22 üzenetére

  Akkor példának itt egy 90nm-en gyártott Xilinx FPGA, ahol a disszipáció csökkentése érdekében alkalmaznak különböző méretű tranzisztorokat.
  
  Optimizing Performance and Leakage
  Our IC designers have many things that they can do to adjust the mix to optimize for certain factors. The Virtex-4 FPGA is the first Platform FPGA designed for high speed and low power.
  
  Low VT transistors are used only where necessary for maximum speed, while the middle thickness of oxide from the triple-oxide process may be used for less aggressive performance with very low leakage. You may use different sizes and types of transistors for performance and function. Combinations are also possible, such as small and medium-sized low VT fast transistors and small and medium-sized middle oxide thickness transistors. It is not a one-size-fits-all procedure.
  
  Xilinx IC designers were given a directive to reduce power, among other things, in the Virtex-4 platform while maintaining the highest system performance. These transistors are used across the various FPGA functions of LUTs, I/O, interconnect, and configuration memory cells. Even within a given FPGA function, all transistors don’t need to be the same, and that is up to the Xilinx IC designers (see Figure 4).
  
  The surprising result of this balancing is that the overall static current in Virtex-4 devices with 90 nm process is reduced by 40% when compared to Virtex-II Pro devices with 130 nm process. Table 1 shows a chart of the weighted average changes to the transistors in the Virtex-4 die compared to Virtex-II Pro die, which allows you to arrive at the reduced transistor leakage in the Virtex-4 FPGA.
  
  [link]

  My other car is an F-14 Tomcat!

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