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• #33 P.H. senior tag Abu85 #31

  Új Válasz 2011-08-17 15:07:30 #33

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  P.H.

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  válasz Abu85 #31 üzenetére

  A másik kérdés, ami bennem felmerült, hogy az rendben van, hogy az AMD GCN-es dGPU-k támogatják majd az x86 virtuális memóriát a CPU pointereken keresztül, de az NV-nek van-e erre licence? Ez bizonytalansági tényező, ami esetlegesen probléma lehet a mixelésnél.

  Ezt megoldották az NV helyett az IOMMU-val (és gondolom, a VT-vel). Bár gyakorlati alkalmazását a virtualizáción kívül még nem láttam, de ez csak egy az IOMMU által nyújtott szolgáltatások közül. A chipset megfelelő részeire ültetett TLB-k tartalma a futó processekének megfelelő, és lehetőséget ad arra, hogy - az eddig a GART által biztosított kernelmemória-hozzáférésen kívül - a device a megfelelő process teljes user-space memóriájához is hozzáférjen, közvetlenül, védetten, azzal a feltétellel, hogy HDD-ről való belapozást nem tud kiváltani.

  [link]

  The I/O Memory Management Unit (IOMMU) is a chipset function that translates addresses used in DMA transactions and protects memory from illegal access by I/O devices.
  The IOMMU can be used to:
  • Replace the existing GART mechanism.
  • Remap addresses above 4GB for devices that do not support 64-bit addressing.
  • Allow a guest OS running under a VMM to have direct control of a device.
  • Provide fine-grain control of device access to system memory.
  • Enable a device direct access to user space I/O.

  2.2.1 Replacing the GART
  The GART is a system facility that performs physical-to-physical translation of memory addresses within a graphics aperture. The GART was defined to allow complex graphical objects, such as texture maps, to appear to a graphics co-processor as if they were located in contiguous pages of memory, even though they are actually scattered across randomly allocated pages by most operating systems. The GART translates all accesses to the graphics aperture, including loads and stores executed by the host CPU as well as memory reads and writes performed by I/O devices. Only accesses whose system physical addresses are within the GART aperture are translated; however, the results of the translation can be any system physical address.

  Unlike the GART, the IOMMU translates only memory accesses by I/O devices. However, with appropriate programming, a host OS can use the IOMMU as a functional equivalent of the GART. First, the host OS must set up its own page tables to perform translations of host CPU accesses formerly translated by the GART. Then, to set up the same translations for I/O device-initiated accesses, the host OS must:
  • Construct I/O page tables that specify the desired translations.
  • Make an entry in the device table pointing to the newly constructed I/O page tables.
  • Notify the IOMMU of the newly updated device table entry if NPcache=1.
  At this point, all accesses by both the host CPU and the graphics device are mapped to the same pages as they would have been by the GART.

  2.2.4 User Mode Device Accesses
  The IOMMU plays a crucial role in allowing arbitrary I/O devices to be safely controlled by user-level processes, since I/O devices whose memory accesses are translated by the IOMMU can only access pages that are explicitly mapped by the associated I/O page tables. The I/O devices' access can therefore be limited to only those pages to which the user processes legitimately have access.

  Setting up the IOMMU for user-level I/O to an I/O device may be set up similarly to GART emulation with two differences: first, the mappable address range is the entire range of I/O device-generatable addresses, and secondly the operating system is not necessarily required to make exactly equivalent mappings in the CPU page tables (although most likely it will).

  Even with the help of the IOMMU, enabling user level I/O device access involves many design considerations. Protecting and remapping DMA is one part of the problem; the other part is interrupt management, for which the IOMMU provides help.

  As was the case with GART emulation, system software must assess the need to lock in memory all pages that might ever be accessed by an I/O device controlled by a user-level process.

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