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• #504 Raymond félisten P.H. #503

  Új Válasz 2007-05-09 22:44:01 #504

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  Raymond

  félisten

  válasz P.H. #503 üzenetére

  Az eddigi cikkek szerint lesz javitas par dologban amit felhoztal:
  
  Elagazasbecsles
  
  - 512-entry indirect predictor
  - double size return stack
  - tracking more branches (nem talaltam szamot)
  
  Load/Store
  
  ''Barcelona can now re-order loads ahead of other loads, just like Core 2 can. It can also execute loads ahead of other stores, assuming that the processor knows that the two don't share the same memory address. While Intel uses a predictor to determine whether or not the store aliases with the load, AMD takes a more conservative approach. Barcelona waits until the store address is calculated before determining whether or not the load can be processed ahead of it. By doing it this way, Barcelona is never wrong and there's no chance of a mispredict penalty. AMD's designers looked at using a predictor like Intel did but found that it offered no performance improvement on its architecture. AMD can generate up to three store addresses per clock as it has three AGUs (Address Generation Units) compared to Intel's one for stores, so it would make sense that AMD has a bit more execution power to calculate a store address before moving a load ahead of it.''

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