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  • Fiery

    veterán

    válasz Petykemano #15435 üzenetére

    Ha o ugyanaz az ember, akkor igy mar azert kicsit egyertelmubb a dolog.

    Senior Design Engineer
    AMD

    June 2013 – Present (2 years 5 months)|Sunnyvale, California

    • Synthesis, Place and route Lead for decode unit in AMD's next-gen CPU core
    • Owned and coded RTL for various modules within the decode unit
    • Member of methodology team which defined the physical design flows for the CPU cores team

    Design Engineer 2
    AMD

    July 2010 – June 2013 (3 years)|Sunnyvale, California

    • Owned a custom block design on 28nm Excavator core.
    • Successfully converged on timing , power and analysis to tapeout the design in 28nm.
    • Created a "lef parser" tool to automate lef porting from one technology to another which speeded up turnaround time for design.
    • Member of timing integration team, performed full core STA for timing closure
    • As part of power methodology team, developed algorithm and flow to swap Vt types to save on leakage power at low technology nodes with minimal impact to timing
    • Derived the "stack-inverter" concept to save leakage power at sub-micron technologies.
    • Successfully taped out 32nm PileDriver Core.

    Valojaban konkretan azt irja le, hogy a 28 nanos Excavator es a 32 nanos Piledriver tapeoutjaban vett reszt, es az uj generacios AMD procik (Zen? K12? mindketto? egyik se? ki tudja) tervezeseben. Ez me'g mindig jelentheti azt, hogy az AMD megkerte, hogy vegye ki a tapeoutot a Zen+K12 kapcsan a felsorolasbol -- vagy azt, hogy valojaban a mostani allapot fedi a valosagot, es a Zen+K12 tervezeseben vett reszt az ember, de a sikeres tapeoutban (me'g) nem.

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