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Processing core

- ARM926EJ-S 32 bit processor core for controller functions. The ARM926EJ-S includes an MMU, and the
Jazelle Java extension for Java acceleration and a MOVE co-processor to accelerate Motion Estimation
algorithms with based video encoding schemes..
- TEAKLite DSP core

ARM9-Memory

- 32k Byte Boot ROM on the AHB
- 128k Byte SRAM on the AHB, flexibly usable as program or data RAM
- 32k Byte Instruction Cache
- 32k Byte Data Cache
- 8k Byte Instruction Tightly coupled Memory (I-TCM)
- 8k Byte Data tightly coupled memory (D-TCM)

TEAKLite®-Memory

- 120k x 16bit Program ROM
- 8k x 16bit Program RAM
- 72k x 16bit Data ROM
- 48k x 16bit Data XRAM
- 5k x 16bit Data YRAM
- Incremental Redundancy(IR) Memory of 35904 words of 16bit

Shared Memory Block

1.5K x 32bit Shared RAM(dual ported) between controller system and TEAKLite®.

Controller Bus system

The processor cores and their peripherals are connected by powerful buses.
- Multi-layer AHB for connecting the ARM and the other master capable building blocks with the internal
and external memories and with the peripheral buses.
- An FPI-Bus for connecting GSM peripherals, called hereafter FPI3 bus.
- A controller FPI bus for connecting the low performance controller peripherals such as keypad
etc. called hereafter fPI2 bus.
- FPI2 and FPI3 are connected asynchronously to the AHB buses. 1 DMA controller with 8channels
offloads the controller from data transfers.
- 2 AHB Lite buses for connecting multi-media and high performance peripherals, called AHB_PER1 and
AHB_PER2 hereafter. These peripheral buses are connected to the multi-layer AHB ‘backbone’ by
asynchronous, burst capable AHB2AHB bridges which are shared between accessing masters.
- The DMA controller is enabled to access AHB_PER1 by use of its first master interface and AHB_PER2 by
its second master interface.

TEAKLite® Bus System

- 1 TEAKLite® data bus for connecting the TEAKLite® data memory and the TEAKLite® peripherals. Also the
data bus is connected into the controller system via shared RAMs to the FPI3 bus.
- 1 TEAKLite® program bus for connecting the TEAKLite® program memory to the TEAKLite®.

Clock system

The clock system allows widely independent selection of frequencies for the essential parts of the SGOLD
®3H. Thus power consumption and performance can be optimized for each application.

Functional Hardware block

- CPU and DSP Timers
- MOVE coprocessor performing motion estimation for video encoding algorithms
(H.263, MPEG-4)
- Programmable PLL with four additional phase shifters for system clock generation
- GSM Timer Module that off-loads the CPU from radio channel timing
- GMSK / 8-PSK Modulator according to GSM-standard 05.04 (5/2000)
· GMSK Modulator: gauss-filter with B*T=0.3
· EDGE Modulator: 8PSK-modulation with linearized GMSK-Pulse-Filter
- Hardware accelerators for equalizer and channel decoding.
- Incremental Redundancy memory for EDGE class 12 support
- A5/1, A5/2, A5/3 Cipher unit
- GEA1, GEA2, GEA3 Cipher Unit to support GPRS data transmission
- f8 and f9 Cipher unit
- Advanced static and dynamic power management features including TDMA-Frame
synchronous low-power mode and enhanced CPU modes(idle and sleep modes)
- 2D engine for support of image processing and 2D graphics applications. The 2D engine is tightly
coupled to the display interface. The resulting building block consisting of 2D engine and Display
interface is called Display Content Controller (DCC)
- Security crypto box supporting
· AES, DES, 3 DES
· Hash function
· RSA acceleration
· Secret Root Key (e-fuse) and Key Management
· True Random Number Generator
- Sample Rate Converter (SRC) for audio up-sampling
- Comprehensive static and dynamic Power Management
· Various frequency options during operation mode
· 32 kHz clock in standby mode
· Sleep control in standby mode
· RAMs and ROMs in power save mode during standby mode
· Additional leakage current reduction in standby mode possible by switching off for the TEAKLitre®
subsystem.
- Extensive debug support for the controller and the DSP system
· OCDS level 2+ (run control, non-intrusive program flow trace and limited data flow trace) for ARM
· OCDS level 1+ (run control, limited program flow trace) for the TEAKLite®
· Multi-core debug support
· 4 Monitor pins for important internal signals and most pad signals
· Cerberus debugging unit
- 2 General Purpose Timers with 3 32-bit timers
- Serial number
- A real time clock with alarm functions
- 2 capture/compare units with 16 channels. One channel active during sleep mode.

3G Coprocessor Subsystem

- ARM7 TRMI-S
· 240 kByte Instruction RAM
· 64 kByte Data RAM
· 8 kByte Boot ROM
- 20kByte Communication RAM
- HW accelerators for
· Transmit Path
· Inner and Outer Receiver for Release5 incl. HSDPA

Charging control

Charging method : CC-CV
Charger output voltage : 5.1 V
Charging time : 2h 20m
Charging current : 620 mA
CV voltage : 4.2 V
Cutoff current : 117 mA
Full charge indication current (icon stop current) : 117 mA
Recharge voltage : 4.15 V
Low battery alarm
Idle : 3.45 V ~ 3.31 V
Dedicated : 3.45 V ~ 3.3 V
Low battery alarm interval
Idle : 3 min
Dedicated : 1 min
Switch-off voltage : 3.31 V
Charging temperature adc range
~ -20℃ : low charging voltage operation (3.6 V ~ 3.9 V) .
-20℃ ~ 60℃ : standard charging (up to 4.2 V)
60℃~ : low charging voltage operation (3.6V ~ 3.9V)

Audio amplifier

KM900 use external AMP(MAX9722BETE).
MAX9722BETE combines a high efficiency Class D audio power amplifier with a stereo Class AB capacitor-less
Direct Drive headphone amplifier.
MAX9722BETE delivers up to 70mW from a 3.7V supply into an 16ohm load and up to 130mW into a 32ohm
with 87% efficiency to extend battery life.

WLAN/Bluetooth/FM (LBEH19UNBC)

WLAN

The KM900 supports single-band 2.4GHz IEEE802.11b/g standardization. The WLAN module which is
consisted of the BCM4325 single chip device provides for the highest level of integration for a mobile
or handheld wireless system, with integrated IEEE802.11TM b/g (MAC/baseband/radio). The BCM4325’s
integrated CMOS WLAN 2.4GHz power amplifier provide sufficient output power to meet
the need of most WLAN devices. The interface between PMB8878 and WLAN module is the standard
interfaces SDIO v1.2 (4-bit and 1-bit).

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